Graphics systems sometimes employ tiling to store pixel data in a graphics memory. Tiling is a memory addressing mode in which a square or rectangular pixel area is mapped into consecutive addresses to improve memory access coherence. The number of pixels associated with an individual tile may vary depending upon the design of the graphics system. A tile commonly includes different types of graphical data. In some graphics processing units (GPUs), tiles are used to store combined z data (also known as depth data) and stencil data (also known as “s” data). A common tile format is 24 bit Z data and 8 bit stencil (“Z24S8”).
A drawback of conventional tiling techniques is that the reading, writing, clearing, and compression of tile data is not as efficient as desired. In some graphics systems, such as graphics systems with 24 bit z data, z data may not pack efficiently into tiles. A similar problem exists in regards to graphics systems storing 24 bit color data (i.e., red-green-blue RGB color space data) and associated alpha (opacity) data.
One problem with conventional tiling techniques is related to storing and accessing tile data from a partitioned memory. Graphics systems increasingly use partitioned memory systems to provide efficient memory accesses when the memory system is wide and consists of multiple memory chips. FIG. 1 illustrates a partitioned memory described in more detail in U.S. patent application Ser. No. 09/687,453, entitled “Controller For A Memory System Having Multiple Partitions,” commonly assigned to the assignee of the present invention, the contents of which are hereby incorporated by reference. In the partitioned graphics memory of FIG. 1, the physical memory is a memory array 24 comprising two or more operable partitions 26a, 26b, 26c, and 26d. Each memory partition has its own individual bus 28a, 28b, 28c, and 28d connecting it to a memory controller 30. The memory controller 30 includes queues 32, 34, 36, 38, 40, 42, 44, and 46 and control logic (not shown) to determine routing to the partitions such that the partitioned memory appears as a non-partitioned memory to clients, such as host 12, texture 14, z read/write module 16, color module 18, or display 20.
There are a number of challenges to supporting tiling in a multi-partitioned memory system. First, each tile must be wholly contained in a partition. Another problem associated with tiled memories is providing efficient storage and memory access in graphics systems supporting different data types and modes of operation. GPUs are increasingly designed to support different data types and different rendering modes. For example, as described in U.S. patent Ser. No. 10/740,229, a graphics system may support modes in which only one type of data, such as z data, is accessed from a tiled memory. However, conventional tiling techniques tend to have drawbacks when used in graphics systems that support different data types and modes of operation. It is difficult to simultaneously achieve a high packing efficiency and good memory access efficiency. In particular, it is difficult to provide efficient packing and bandwidth for pixel data types containing z (with and without stencil) and color (with and without alpha).
Therefore, what is desired is an improved apparatus, system, and method for utilizing tiles in a graphics memory, including partitioned and non-partitioned graphics memories.